Japanese Inventors Develop Cache Memory with Valid Bits
Copyright © Targeted News Service 2008
2008-10-29
ALEXANDRIA, Va., Oct. 29 -- Masashi Fujita of Tokyo, and Yoshiyuki Kurokawa of Kanagawa, Japan, have developed a semiconductor device.
According to the abstract released by the U.S. Patent & Trademark Office: "A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. . . .
According to the abstract released by the U.S. Patent & Trademark Office: "A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. . . .