Wednesday - June 17, 2026

On-Chip Digitally Controlled Error Rate-Locked Loop for Error Resilient Edge Artificial Intelligence

2026-06-16

ALEXANDRIA, Virginia, June 16 -- INTEL CORPORATION, Santa Clara, California has been assigned a patent (No. US 12656843 B2, initially filed March 15, 2022) developed by Hechen Wang, Portland, Oregon, for "On-chip digitally controlled error rate-locked loop for error resilient edge artificial intelligence." . . .

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On-Chip Digitally Controlled Error Rate-Locked Loop for Error Resilient Edge Artificial Intelligence

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