GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform
January 10, 2024
January 10, 2024
SAN JOSE, California, Jan. 10 -- Cadence Design Systems, a provider of electronic design automation and semiconductor intellectual property, issued the following news release:
Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which involves a memory-on-logic configuration achieved with a wafer-on-wafer (WoW) structure using a flip-chip chip scale package, was cr . . .
Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which involves a memory-on-logic configuration achieved with a wafer-on-wafer (WoW) structure using a flip-chip chip scale package, was cr . . .