Saturday - December 21, 2024

Multi-Input Threshold Gate Having Stacked and Folded Non-Planar Capacitors

2024-12-17

ALEXANDRIA, Virginia, Dec. 17 -- KEPLER COMPUTING INC., San Francisco, California has been assigned a patent (No. US 12171103 B1, initially filed March 14, 2022) developed by six inventors Rajeev Kumar Dokania, Beaverton, Oregon; Amrita Mathuriya, Portland, Oregon; Debo Olaosebikan, San Francisco, California; Tanay Gosavi, Portland, Oregon; Noriyuki Sato, Hillsboro, Oregon; and Sasikanth Manipatruni, Portland, Oregon, for "Multi-input threshold gate having stacked and folded non-planar capacito . . .

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Multi-Input Threshold Gate Having Stacked and Folded Non-Planar Capacitors

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