Thursday - December 26, 2024

3D Memory With Conductive Dielectric Channel Integrated With Logic Access Transistors

2024-10-29

ALEXANDRIA, Virginia, Oct. 29 -- TOKYO ELECTRON LIMITED, Tokyo, Japan has been assigned a patent (No. US 12133387 B2, initially filed Dec. 20, 2021) developed by three inventors Mark I. Gardner, Albany, New York; H. Jim Fulford, Albany, New York; and Partha Mukhopadhyay, Albany, New York, for "3D memory with conductive dielectric channel integrated with logic access transistors." . . .

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3D Memory With Conductive Dielectric Channel Integrated With Logic Access Transistors

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