Friday - December 27, 2024

Apparatus With Selectable Majority Gate and Combinational Logic Gate Outputs

2024-10-22

ALEXANDRIA, Virginia, Oct. 22 -- KEPLER COMPUTING INC., San Francisco, California has been assigned a patent (No. US 12126339 B2, initially filed Nov. 16, 2022) developed by seven inventors Sasikanth Manipatruni, Portland, Oregon; Rafael Rios, Austin, Texas; Ikenna Odinaka, Durham, North Carolina; Robert Menezes, Portland, Oregon; Rajeev Kumar Dokania, Beaverton, Oregon; Ramamoorthy Ramesh, Moraga, California; and Amrita Mathuriya, Portland, Oregon, for "Apparatus with selectable majority gate . . .

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Apparatus With Selectable Majority Gate and Combinational Logic Gate Outputs

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