Sunday - June 2, 2024

Memory Device Having 2-Transistor Vertical Memory Cell and Wrapped Data Line Structure

2024-04-02

ALEXANDRIA, Virginia, April 2 -- MICRON TECHNOLOGY, INC., Boise, Idaho has been assigned a patent (No. US 11950426 B2, initially filed March 27, 2023) developed by six inventors Kamal M. Karda, Boise, Idaho; Eric S. Carman, San Francisco, California; Karthik Sarpatwari, Boise, Idaho; Durai Vishak Nirmal Ramaswamy, Boise, Idaho; Richard E Fackenthal, Carmichael, California; and Haitao Liu, Boise, Idaho, for "Memory device having 2-transistor vertical memory cell and wrapped data line structure." . . .

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Memory Device Having 2-Transistor Vertical Memory Cell and Wrapped Data Line Structure

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